TY - JOUR

T1 - Partial dynamic element matching technique for digital-to-analog converters used for digital harmonic-cancelling sine-wave synthesis

AU - Aluthwala, Pasindu Dissan

AU - Weste, Neil

AU - Adams, Andrew

AU - Lehmann, Torsten

AU - Parameswaran, Sri

PY - 2017/2

Y1 - 2017/2

N2 - Digital harmonic-cancelling sine-wave synthesizers (DHSSs) use a 47 year old concept, recently revived as a power and area efficient solution for on-chip sine-wave synthesis. The operation of a DHSS involves amplitude scaling and summing a set of square-waves to produce a sampled sine-wave. The circuit which performs the scaling and summing operation is referred to as the harmonic-cancelling digital-to-analog converter (HC-DAC). Unlike a regular DAC whose amplitude weights are defined by powers of two, an HC-DAC's amplitude weights are defined by a sine function. Thus, HC-DACs present intriguing design problems which cannot be solved using the conventional knowledge gathered from designing regular DACs. One such problem is managing the effect of mismatch between unit-elements in HC-DACs. This paper proposes a partial dynamic element matching (DEM) technique tailored for HC-DACs, which reduces the effect of mismatch, while preserving the power and area efficiency of DHSSs. The effectiveness of the DEM technique is evaluated using a DHSS circuit fabricated in an STMicroelectronics 130 nm CMOS technology. Test results show that applying the DEM technique increased the figure-of-merit of the DHSS by 40% at 2 MHz output frequency.

AB - Digital harmonic-cancelling sine-wave synthesizers (DHSSs) use a 47 year old concept, recently revived as a power and area efficient solution for on-chip sine-wave synthesis. The operation of a DHSS involves amplitude scaling and summing a set of square-waves to produce a sampled sine-wave. The circuit which performs the scaling and summing operation is referred to as the harmonic-cancelling digital-to-analog converter (HC-DAC). Unlike a regular DAC whose amplitude weights are defined by powers of two, an HC-DAC's amplitude weights are defined by a sine function. Thus, HC-DACs present intriguing design problems which cannot be solved using the conventional knowledge gathered from designing regular DACs. One such problem is managing the effect of mismatch between unit-elements in HC-DACs. This paper proposes a partial dynamic element matching (DEM) technique tailored for HC-DACs, which reduces the effect of mismatch, while preserving the power and area efficiency of DHSSs. The effectiveness of the DEM technique is evaluated using a DHSS circuit fabricated in an STMicroelectronics 130 nm CMOS technology. Test results show that applying the DEM technique increased the figure-of-merit of the DHSS by 40% at 2 MHz output frequency.

KW - DAC

KW - DEM

KW - digital sinusoid signal generation

KW - harmonic rejection

KW - low harmonic distortion

UR - http://www.scopus.com/inward/record.url?scp=84994275608&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2016.2613938

DO - 10.1109/TCSI.2016.2613938

M3 - Article

AN - SCOPUS:84994275608

VL - 64

SP - 296

EP - 309

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

IS - 2

ER -